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M28C16B M28C17B
16 Kbit (2K x 8) Parallel EEPROM With Software Data Protection
PRELIMINARY DATA
s s
Fast Access Time: 90 ns at VCC=5V Single Supply Voltage: - 4.5 V to 5.5 V for M28CxxB - 2.7 V to 3.6 V for M28CxxB-W
s s
Low Power Consumption Fast BYTE and PAGE WRITE (up to 64 Bytes) - 3 ms at VCC=4.5 V - 5 ms at VCC=2.7 V
s
Enhanced Write Detection and Monitoring: - Data Polling - Toggle Bit - Page Load Timer Status
PLCC32 (K)
s s s s
JEDEC Approved Bytewide Pin-Out Software Data Protection 100000 Erase/Write Cycles (minimum) Data Retention (minimum): 40 Years
DESCRIPTION The M28C16B and M28C17B devices consist of 2048x8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics' proprietary single polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply.
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
A0-A10 DQ0-DQ7 W E G RB VCC VSS Address Input
11 A0-A10
8 DQ0-DQ7
Data Input / Output Write Enable Chip Enable Output Enable Ready/Busy (M28C17B only) Supply Voltage Ground
W E G
M28C16B M28C17B RB (M28C17B only)
VSS
AI02816
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M28C16B, M28C17B
Figure 2A. PLLC Connections
NC NC VCC W NC A7 NC
Figure 2B. PLLC Connections
NC RB VCC W NC 1 32 A8 A9 NC NC G A10 E DQ7 DQ6 A6 A5 A4 A3 A2 A1 A0 NC DQ0 A8 A9 NC NC G A10 E DQ7 DQ6 M28C17B 25 17 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5
AI02817 AI02830
1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0
9
M28C16B
25
9
17 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
The M28C17B is like the M28C16B in every way, except that it has an extra ready/busy (RB) output. The device has been designed to offer a flexible microcontroller interface, featuring software handshaking, with Data Polling and Toggle Bit. The device supports a 64 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm. SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A10). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. Write Enable (W). The Write Enable input controls whether the addressed location is to be read, from or written to. Ready/Busy (RB). Ready/Busy (on the M28C17B only) is an open drain output that can be used to detect the end of the internal write cycle.
DEVICE OPERATION In order to prevent data corruption and inadvertent write operations, an internal VCC comparator inhibits the Write operations if the V CC voltage is lower than V WI (see Table 4A). Once the voltage applied on the VCC pin goes over the VWI threshold (V CC>VWI), write access to the memory is allowed after a time-out t PUW, as specified in Table 4A. Further protection against data corruption is offered by the E and W low pass filters: any glitch, on the E and W inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. Read The device is accessed like a static RAM. When E and G are low, and W is high, the contents of the addressed location are presented on the I/O pins. Otherwise, when either G or E is high, the I/O pins revert to their high impedance state. Write Write operations are initiated when both W and E are low and G is high. The device supports both W-controlled and E-controlled write cycles (as shown in Figure 11 and Figure 12). The address is latched during the falling edge of W or E (which ever occurs later) and the data is latched on the rising edge of W or E (which ever occurs first). After a delay, tWLQ5H, that cannot be shorter than the value specified in Table 10A, the internal write cycle starts. It continues, under internal timing control, until the write operation is complete. The commencement of this period can be detected by reading the Page Load Timer Status on DQ5. The
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A7 NC
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M28C16B, M28C17B
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG VCC VIO VI VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) 2 Value -40 to 125 -65 to 150 -0.3 to 6.5 -0.6 to VCC+0.6 -0.3 to 6.5 4000 Unit C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
Figure 3. Block Diagram
E G W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A10 (Page Address)
ADDRESS LATCH
16K ARRAY
A0-A5
ADDRESS LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING
AI02818
DQ0-DQ7
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M28C16B, M28C17B
Table 3. Operating Modes 1
Mode Stand-by Output Disable Write Disable Read Write Chip Erase E 1 X X 0 0 0 G X 1 X 0 1 V W X X 1 1 0 0 DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Out Data In Hi-Z
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V 5%.
end of the cycle can be detected by reading the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6. Page Write The Page Write mode allows up to 64 bytes to be written on a single page in a single go. This is achieved through a series of successive Write operations, no two of which are separated by more than the tWLQ5H value (as specified in Table 10A). The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of: 1/t WLQ5H. The internal write cycle can start at any instant after tWLQ5H. Once initiated, the write operation is internally timed, and continues, uninterrupted, until completion. All bytes must be located on the same page address (A10-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not executed. As with the single byte Write operation, described above, the DQ5, DQ6 and DQ7 lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle. Software Data Protection (SDP) The device offers a software-controlled write-protection mechanism that allows the user to inhibit all write operations to the device. This can be useful for protecting the memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). By default, the device is shipped in the "unprotected" state: the memory contents can be freely changed by the user. Once the Software Data Protection Mode is enabled, all write commands are
Table 4A. Power-Up Timing1 for M28CxxB (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 3.0 Min. Max. 1 10 4.2 Unit s ms V
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28CxxB-W (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 1.5 Min. Max. 1 15 2.5 Unit s ms V
Note: 1. Sampled only, not 100% tested.
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M28C16B, M28C17B
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Write AAh in Address 555h Page Write Timing (see note 1) Page Write Timing (see note 1) Write AAh in Address 555h
Write 55h in Address 2AAh
Write 55h in Address 2AAh
Write A0h in Address 555h
Write A0h in Address 555h Write is Enabled
SDP is set
Physical Page Write Instruction
Page Write (1 up to 64 bytes)
SDP Enable Algorithm
Write to Memory When SDP is SET
AI02819
Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations.
ignored, and have no effect on the memory contents. The device remains in this mode until a valid Software Data Protection disable sequence is received. The device reverts to its "unprotected" state. The status of the Software Data Protection (enabled or disabled) is represented by a non-volatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Similarly to disable the Software Data Protection, the user has to write specific data bytes into six dif-
ferent locations, as shown in Figure 6. This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism.
Figure 6. Software Data Protection Disable Algorithm
Write AAh in Address 555h
Write 55h in Address 2AAh
Figure 5. Status Bit Assignment
Page Write Timing
Write 80h in Address 555h
Write AAh in Address 555h DQ7 DP DQ6 TB DQ5 PLTS DQ4 Hi-Z DQ3 Hi-Z DQ2 Hi-Z DQ1 Hi-Z DQ0 Hi-Z Write 55h in Address 2AAh
DP TB PLTS Hi-Z
= Data Polling = Toggle Bit = Page Load Timer Status = High impedance
AI02815
Write 20h in Address 555h
Unprotected State
AI02820
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M28C16B, M28C17B
Figure 7. Chip Erase AC Waveforms
tWHEH E
G
tGLWH W tELWL tWLWH2 tWHRH
AI01484B
Table 5. Chip Erase AC Characteristics1 (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V)
Symbol tELWL tWHEH tWLWH2 tGLWH tWHRH Parameter Chip Enable Low to Write Enable Low Write Enable High to Chip Enable High Write Enable Low to Write Enable High Output Enable Low to Write Enable High Write Enable High to Write Enable Low Test Condition G = VCC + 7V G = VCC + 7V G = VCC + 7V G = VCC + 7V G = VCC + 7V Min. 1 0 10 1 3 Max. Unit s ns ms s ms
Note: 1. Sampled only, not 100% tested.
When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). The sequence is as shown in Figure 4. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). Software Chip Erase The contents of the entire memory are erased (set to FFh) by holding Chip Enable (E) low, and holding Output Enable (G) at VCC+7.0V. The chip is cleared when a 10 ms low pulse is applied to the Write Enable (W) signal (see Figure 7 and Table 5 for details). Status Bits The devices provide three status bits (DQ7, DQ6 and DQ5), for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6 and DQ5 (but only during programming cycle,
once a byte or more has been latched into the memory). Data Polling bit (DQ7). The internally timed write cycle starts after tWLQ5H (defined in Table 10A) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6). The device offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 toggles from '0' to '1' and '1' to '0' (the first read value being '0') on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5). An internal timer is used to measure the period between suc-
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Table 6A. Read Mode DC Characteristics for M28CxxB (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
Symbol ILI ILO ICC 1 ICC1 1 ICC2 1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs) Supply Current (Stand-by) TTL Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 Test Condition 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIL , f = 5 MHz E = VIL, G = VIL , f = 5 MHz E = VIH E > VCC - 0.3V -0.3 2 Min. Max. 10 10 30 25 1 100 0.8 VCC + 0.5 0.4 Unit A A mA mA mA A V V V V
Note: 1. All inputs and outputs open circuit.
Table 6B. Read Mode DC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol ILI ILO ICC 1 ICC2 1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -400 A 0.8 VCC E > VCC - 0.3V -0.3 2 10 20 0.6 VCC + 0.5 0.2 VCC mA A V V V V Test Condition 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V Min. Max. 10 10 8 Unit A A mA
Note: 1. All inputs and outputs open circuit.
cessive Write operations, up to t WLQ5H (defined in Table 10A). The DQ5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). The DQ5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array).
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M28C16B, M28C17B
Table 7. Input and Output Parameters 1 (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0 V VOUT = 0 V Min. Max. 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 20 ns 0.4 V to 2.4 V 0.8 V to 2.0 V
Figure 8. AC Testing Input Output Waveforms
Figure 9. AC Testing Equivalent Load Circuit
IOL 2.4V 2.0V 0.8V DEVICE UNDER TEST IOH CL = 100pF OUT
0.4V
AI02821
CL includes JIG capacitance
AI02102B
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M28C16B, M28C17B
Table 9A. Read Mode AC Characteristics for M28CxxB (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
M28CxxB Symbol Alt. Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -90 Max 90 90 40 40 40 0 0 0 Min -12 Max 120 120 45 45 45 ns ns ns ns ns ns Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 9B. Read Mode AC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
M28CxxB-W Symbol Alt. Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -12 Max 120 120 80 45 45 0 0 0 Min -15 Max 150 150 80 50 50 ns ns ns ns ns ns Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
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M28C16B, M28C17B
Table 10A. Write Mode AC Characteristics for M28CxxB (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
M28C17B Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out After the Last Byte Write Write Cycle Time Data Valid before Write Enable High Data Valid before Chip Enable High 50 50 E = VIL, G = VIH G = VIH, W = VIL 50 0 0 0 0 0 0 50 50 100 3 Test Condition Min E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 50 50 1 1 Max ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns Unit
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M28C16B, M28C17B
Table 10B. Write Mode AC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
M28C17B-xxW Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after the last byte write Write Cycle Time Data Valid before Write Enable High Data Valid before Chip Enable High 50 50 E = VIL, G = VIH G = VIH, W = VIL 100 0 0 0 0 0 0 50 100 100 5 1000 Test Condition Min E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 100 100 1 1 1000 Max ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns Unit
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M28C16B, M28C17B
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A10 tAVQV E tGLQV G tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA OUT Hi-Z
AI02822
Note: 1. Write Enable (W) = VIH
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A10 tAVWL E tELWL G tGHWL W tWLDV DQ0-DQ7 DATA IN tDVWH RB tWHRL
AI02823
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWHWL
tWHDX
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M28C16B, M28C17B
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A10 tAVEL E tGHEL G tWLEL W tELDV DQ0-DQ7 DATA IN tDVEH RB tEHRL
AI02824
VALID tELAX
tELEH
tEHGL
tEHWH
tEHDX
Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A10 Addr 0 Addr 1 Addr 2 Addr n
E
G tWHWL W tWLWH DQ0-DQ7 (in) Byte 0 Byte 1 Byte 2 Byte n
DQ5 (out) tWHRL RB
AI02825
tWLQ5H tQ5HQ5X
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M28C16B, M28C17B
Figure 14. Software Protected Write Cycle Waveforms
G
E tWLWH W tAVEL A0-A5 tWHDX A6-A10 555h tDVWH DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63
AI02826
tWHWL
tWHWH
tWLAX Byte Address
2AAh
555h
Page Address
Note: 1. A10 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E are both low.
Figure 15. Data Polling Sequence Waveforms
A0-A10 Address of the last byte of the Page Write instruction
E
G
W
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
Last WRITE
Internal Write Sequence
Ready
AI02827
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M28C16B, M28C17B
Figure 16. Toggle Bit Sequence Waveforms
A0-A10
E
G
W
DQ6
(1)
Last WRITE
TOGGLE Internal Write Sequence
Ready
AI02828
Note: 1. The Toggle Bit is first set to `0'.
Table 11. Ordering Information Scheme
Example: M28C16 - 120 W K 6 TR
Ready/Busy 16 17 Pin 1 = Not Connected Pin 1 = Ready/Busy TR
Option Tape and Reel Packing
Speed 90 120 150 90 ns (5V range only) 120 ns 150 ns (3V range only) 1 6
Temperature Range 0 C to 70 C -40 C to 85 C
Operating Voltage blank 4.5 V to 5.5 V W 2.7 V to 3.6 V K
Package PLCC32
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M28C16B, M28C17B
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symbol A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Typ. Min. 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ. inches Min. 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
Figure 17. PLCC (K)
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Note: 1. Drawing is not to scale.
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M28C16B, M28C17B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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